1. Field of the Invention
The present invention relates to a thin film transistor of a TFT-LCD and a method for fabricating the same, and more particularly, to a fabrication method of thin film transistors using four photolithography-etching processes (4 PEP).
2. Description of the Prior Art
A thin film transistor liquid crystal display (TFT-LCD) utilizes many thin film transistors arranged in a matrix as switches for driving liquid crystal molecules to produce brilliant images after cooperating with other elements such as capacitors and bonding pads. The advantages of the TFT-LCD include portability, low power consumption, and low radiation. Therefore, the TFT-LCD is widely used in various portable products, such as notebooks, personal data assistants (PDA), etc. Moreover, the TFT-LCD replaces the CRT monitor in desktop computers gradually.
When simplifying the process for fabricating TFT-LCDs, a fabrication process of the TFT-LCD using only four photolithography-etching processes (4 PEP) is widely applied. Please refer to FIG. 1 to FIG. 6 of schematic diagrams of a 4 PEP fabrication process of a TFT-LCD according to a prior art method. As shown in FIG. 1, the TFT-LCD is fabricated on a surface of a glass substrate 10, and the surface of the substrate 10 comprises a transistor area 13, a capacitor area 14, a first conductive line area 11 and a second conductive line area 12, therein the first conductive line area 11 could be a scan line and the second conductive line area 12 could be a data line. The process first forms a first metal layer (not shown) on the surface of the substrate 10, and then a first PEP is performed to define a pattern of the first metal layer so as to form a first conductive line 20, a gate electrode 16 of a thin film transistor, and a capacitor bottom electrode 18, respectively, in the first conductive line area 11, in the transistor area 13 and in the capacitor area 14.
As shown in FIG. 2, an insulating layer 22, a semiconductor layer 24, a doped silicon layer 26, and a second metal layer 28 are sequentially formed on the surface of the substrate 10 covering the patterned first metal layer. Then, as shown in FIG. 3, a photoresist layer 30 is formed on the surface of the substrate 10, and a second PEP is performed to remove a portion of the second metal layer 28, the doped silicon layer 26, and the semiconductor layer 24 not covered by the photoresist layer 30 until a surface of the insulating layer 22 is exposed. Consequently, a second conductive line 21, the thin film transistor, and the capacitor are formed, respectively, in the second conductive line area 12, in the capacitor area 13, and in the capacitor area 14. Simultaneously, the second metal layer 28, the doped silicon layer 26, and the semiconductor layer 24 in the first conductive line area 11 are removed. Therein, the second metal layer 28 is a capacitor top electrode.
As shown in FIG. 4, an ashing process is performed to remove a portion of the photoresist layer 30 so as to define a channel area 31 of the thin film transistor. The remaining photoresist layer is used as a mask to remove the second metal layer 28 and the doped silicon layer 26 within the channel area 31. Consequently, the channel area 31 separates both the second metal layer 28 and the doped silicon layer 26 into two sides, and the two sides of the second metal layer 28 and the doped silicon layer 26 are respectively used as a source electrode 32 and a drain electrode 34 of the thin film transistor. After that, as shown in FIG. 5, a stripping process is performed to completely remove the remaining photoresist layer, and then a passivation layer 36 is formed on the surface of the substrate 10. A third PEP is performed to form a first contact hole 40 in the passivation layer 36 positioned above the drain electrode 34, a second contact hole 41 in the passivation layer 36 positioned above the capacitor top electrode, a third contact hole 42 in the passivation layer 36 positioned above the second metal layer 28 of the second conductive line area 12, and a fourth contact hole 43 in both the passivation layer 36 and the insulating layer 22 of the first conductive line area 11, respectively. Therefore, a portion of the drain electrode 34, a portion of the capacitor top electrode, a portion of the second conductive line 21, and a portion of the first conductive line 20 are exposed because of the formation of the contact holes 40, 41, 42, 43.
Finally, as shown in FIG. 6, a fourth PEP is performed to simultaneously form a patterned transparent conductive layer 44 on a surface of the passivation layer 36 positioned above the drain electrode 34, on a surface of the passivation layer 36 positioned above the capacitor top electrode, on a surface of the passivation layer 36 of the second conductive line area 12, and on a surface of the passivation layer 36 and the first insulating layer 22 of the first conductive line area 11. Furthermore, the transparent conductive layer 44 is connected with the drain electrode 34, the capacitor top electrode, the second conductive line 21, and the first conductive line 20, respectively, through the first contact hole 40, the second contact hole 41, the third contact hole 42, and the fourth contact hole 43. The fabrication process of the TFT-LCD according to the prior art method only uses four photolithography etching processes and substantially simplifies the fabrication process, however, the second metal layer 28 and the semiconductor layer 24 are simultaneously formed by performing the second PEP according to the prior art method. In detail, the pattern of the semiconductor layer 24 is the same as the second metal layer 28, as shown in FIG. 6, and the semiconductor layer is formed under the second metal layer 28. Consequently, when back light of the TFT-LCD passes through a polarizer (not shown in FIG. 6), the substrate 10, and the insulating layer 22 and directly illuminates the semiconductor layer 24 of the thin film transistor not covered by the gate electrode 16 within the transistor area, thin film transistors of the TFT-LCD fabricated according to the prior art method produce photo induced leakage current, which critically affects the reliability of products.